行為層作法

module top;

integer ia, ib;
reg a, b;
wire c;

xor x1(c,a,b);

initial
begin
for(ia = 0;ia <= 1;ia = ia + 1)
begin
a=ia;
for(ib = 0;ib <= 1;ib = ib + 1)
begin
b=ib;
#10 $display("a = %d b = %d c = %d", a, b, c);
end
end
end
endmodule

系統時脈模組

１module mux(OUT, A, B, SEL);
２output OUT;
３input A, B, SEL;
４
５not I5 (sel_n SEL);
６and I6 (sel_a, A, SEL);
７and I7 (sel_b, sel_n, B);
８
９or I4 (out, sel_a, sel_b);
10 endmodule

使用Verilog基礎語言

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
always#1 c=a&b;
endmodule
module system_clock(clk);
parameter PERIOD=100;output clk;
reg clk;initialclk=0;
alwaysbegin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
endalways@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule