module top;
integer ia, ib;
reg a, b;
wire c;
xor x1(c,a,b);
initial
begin
for(ia = 0;ia <= 1;ia = ia + 1)
begin
a=ia;
for(ib = 0;ib <= 1;ib = ib + 1)
begin
b=ib;
#10 $display("a = %d b = %d c = %d", a, b, c);
end
end
end
endmodule
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