須訂正

module top;
wire a0, a1, b0, b1;

initial begin

#50 a0=0; a1=0; b0=0; b1=0;
#50 a0=0; a1=0; b0=0; b1=1;
#50 a0=0; a1=0; b0=1; b1=0;
#50 a0=0; a1=0; b0=1; b1=1;
#50 a0=0; a1=1; b0=0; b1=0;
#50 a0=0; a1=1; b0=0; b1=1;
#50 a0=0; a1=1; b0=1; b1=0;
#50 a0=0; a1=1; b0=1; b1=1;
#50 a0=1; a1=0; b0=0; b1=0;
#50 a0=1; a1=0; b0=0; b1=1;
#50 a0=1; a1=0; b0=1; b1=0;
#50 a0=1; a1=0; b0=1; b1=1;
#50 a0=1; a1=1; b0=0; b1=0;
#50 a0=1; a1=1; b0=0; b1=1;
#50 a0=1; a1=1; b0=1; b1=0;
#50 a0=1; a1=1; b0=1; b1=1;
#50 $finish;

end
endmodule


module comparator(out, a0, a1, b0, b1);

input a0, a1, b0, b1;
output out;
wire na1, nb0, nb1, f1, f2, f3, f4,;

not(nb0,b0);
not(nb1,b1);
not(na1,a1);
and i1( f1, nb0, nb1);
and i2( f2, a0, nb0, nb1);
and i3( f3, a0, na1, nb0);
and i4( f4, a0, a1);
or i5( out, f1, f2, f3, f4);

endmodule

延遲 3 2 須訂正

module top;
reg zA, zB;
wire zO, zC1;
and a1(zC, zA, zB);
not a2(zO, zC);

initial begin

#100 zA=1; zB=0;
#100 zA=1; zB=1;
#100 zA=0; zB=1;
#100 zA=0; zB=0;
#100 $finish;

end
endmodule

module AND(C, A, B);
input A, B;
output C;
and (C, A, B);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(A=>C) = (Tpd_0_1, Tpd_1_0);
(B=>C) = (Tpd_0_1, Tpd_1_0);

endspecify
endmodule

module NOt(O, C);
input C;
output O;
not (O, C);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(C=>O) = (Tpd_0_1, Tpd_1_0);


endspecify
endmodule