須訂正

module top;
wire a0, a1, b0, b1;

initial begin

#50 a0=0; a1=0; b0=0; b1=0;
#50 a0=0; a1=0; b0=0; b1=1;
#50 a0=0; a1=0; b0=1; b1=0;
#50 a0=0; a1=0; b0=1; b1=1;
#50 a0=0; a1=1; b0=0; b1=0;
#50 a0=0; a1=1; b0=0; b1=1;
#50 a0=0; a1=1; b0=1; b1=0;
#50 a0=0; a1=1; b0=1; b1=1;
#50 a0=1; a1=0; b0=0; b1=0;
#50 a0=1; a1=0; b0=0; b1=1;
#50 a0=1; a1=0; b0=1; b1=0;
#50 a0=1; a1=0; b0=1; b1=1;
#50 a0=1; a1=1; b0=0; b1=0;
#50 a0=1; a1=1; b0=0; b1=1;
#50 a0=1; a1=1; b0=1; b1=0;
#50 a0=1; a1=1; b0=1; b1=1;
#50 $finish;

end
endmodule


module comparator(out, a0, a1, b0, b1);

input a0, a1, b0, b1;
output out;
wire na1, nb0, nb1, f1, f2, f3, f4,;

not(nb0,b0);
not(nb1,b1);
not(na1,a1);
and i1( f1, nb0, nb1);
and i2( f2, a0, nb0, nb1);
and i3( f3, a0, na1, nb0);
and i4( f4, a0, a1);
or i5( out, f1, f2, f3, f4);

endmodule