延遲 3 2 須訂正

module top;
reg zA, zB;
wire zO, zC1;
and a1(zC, zA, zB);
not a2(zO, zC);

initial begin

#100 zA=1; zB=0;
#100 zA=1; zB=1;
#100 zA=0; zB=1;
#100 zA=0; zB=0;
#100 $finish;

end
endmodule

module AND(C, A, B);
input A, B;
output C;
and (C, A, B);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(A=>C) = (Tpd_0_1, Tpd_1_0);
(B=>C) = (Tpd_0_1, Tpd_1_0);

endspecify
endmodule

module NOt(O, C);
input C;
output O;
not (O, C);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(C=>O) = (Tpd_0_1, Tpd_1_0);


endspecify
endmodule