半加法器((迴圈形式))

module top;
integer ia, ib;
reg a, b;
wire c, s;
and a1(c, a, b);
xor x1(s, a, b);
initial
begin
for(ia=0; ia<=1; ia=ia+1)
begin
a=ia;
for(ib=0; ib<=1; ib=ib+1)
begin
b=ib;
#30 $display("a=%d b=%d C=%d s=%d", a, b, c, s);
end
end
end
endmodule