Not AND(單腳)系統時脈

module top;
wire zA1, zB1;

system_clock #50 s1(zA1);

manf201 s3(zOut, zA1);
endmodule

module manf201(o, A1);
input A1;
output o;
not a2(o, A1);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(A1=>o) = (Tpd_0_1, Tpd_1_0);

endspecify
endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(49*PERIOD / 50) clk = ~clk;
#(PERIOD - 49*PERIOD / 50) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule