Not AND(單腳)系統時脈

module top;
wire zA1, zB1;

system_clock #50 s1(zA1);

manf201 s3(zOut, zA1);
endmodule

module manf201(o, A1);
input A1;
output o;
not a2(o, A1);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(A1=>o) = (Tpd_0_1, Tpd_1_0);

endspecify
endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(49*PERIOD / 50) clk = ~clk;
#(PERIOD - 49*PERIOD / 50) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule

Not AND(雙腳)系統時脈

module top;
wire zA1, zB1;

system_clock #100 s1(zA1);
system_clock #200 s2(zB1);

manf201 s3(zOut, zA1, zB1);
endmodule

module manf201(o, A1, B1);
input A1, B1;
output o;
nand a1(o, A1, B1);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(A1=>o) = (Tpd_0_1, Tpd_1_0);
(B1=>o) = (Tpd_0_1, Tpd_1_0);

endspecify
endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule

RTL <<演算法>> 系統時脈

module top;

wire out;
wire[3:0] in;

system_clock #50 o1(in[0]);
system_clock #100 o2(in[1]);
system_clock #200 o3(in[2]);
system_clock #400 o4(in[3]);

and4_algo v1( out, in);

endmodule


module and4_algo(y_out,x_in);

input[3:0] x_in;
output y_out;
reg y_out;
integer k;

always@(x_in)
begin:and_loop
y_out = 1;
for(k = 0;k <= 3;k = k + 1)
if(x_in[k]==0)
begin
y_out=0;
disable and_loop;
end
end
endmodule


module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule

RTL 結構做法 ~系統時脈~

module top;
wire [3:0] zin;
wire zout;

system_clock #100 s1(zin[0]);
system_clock #200 s2(zin[1]);
system_clock #300 s2(zin[2]);
system_clock #400 s2(zin[3]);

and4_rtl s5(zout, zin);

endmodule

module and4_rtl(y_out, x_in);

input [3:0] x_in;
output y_out;
wire w1, w2;
and a1(w1, x_in[0], x_in[1]);
and a2(w2, x_in[2], x_in[3]);
and a2(y_out, w1, w2);

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule

RTL 矩陣形式 ~系統時脈~

module top;
wire [3:0] zin;
wire zout;

system_clock #100 s1(zin[0]);
system_clock #200 s2(zin[1]);
system_clock #300 s2(zin[2]);
system_clock #400 s2(zin[3]);

and4_rtl s5(zout, zin);

endmodule

module and4_rtl(y_out, x_in);

input [3:0] x_in;

output y_out;

assign y_out = &x_in;

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule

RTL~系統時脈~

module top;
wire zin1, zin2, zin3, zin4;

system_clock #100 s1(zin1);
system_clock #200 s2(zin2);
system_clock #300 s3(zin3);
system_clock #400 s4(zin4);

and4_rtl s5(zout, zin1, zin2, zin3, zin4);

endmodule

module and4_rtl(y_out, x_in1, x_in2, x_in3, x_in4);

input x_in1, x_in2, x_in3, x_in4;

output y_out;

assign y_out = x_in1 & x_in2 & x_in3 & x_in4;

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 5000)
#(PERIOD - 1)
$stop;
endmodule