RTL <<演算法>> 系統時脈

module top;

wire out;
wire[3:0] in;

system_clock #50 o1(in[0]);
system_clock #100 o2(in[1]);
system_clock #200 o3(in[2]);
system_clock #400 o4(in[3]);

and4_algo v1( out, in);

endmodule


module and4_algo(y_out,x_in);

input[3:0] x_in;
output y_out;
reg y_out;
integer k;

always@(x_in)
begin:and_loop
y_out = 1;
for(k = 0;k <= 3;k = k + 1)
if(x_in[k]==0)
begin
y_out=0;
disable and_loop;
end
end
endmodule


module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule