RTL 矩陣形式 ~系統時脈~

module top;
wire [3:0] zin;
wire zout;

system_clock #100 s1(zin[0]);
system_clock #200 s2(zin[1]);
system_clock #300 s2(zin[2]);
system_clock #400 s2(zin[3]);

and4_rtl s5(zout, zin);

endmodule

module and4_rtl(y_out, x_in);

input [3:0] x_in;

output y_out;

assign y_out = &x_in;

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule