RTL~系統時脈~

module top;
wire zin1, zin2, zin3, zin4;

system_clock #100 s1(zin1);
system_clock #200 s2(zin2);
system_clock #300 s3(zin3);
system_clock #400 s4(zin4);

and4_rtl s5(zout, zin1, zin2, zin3, zin4);

endmodule

module and4_rtl(y_out, x_in1, x_in2, x_in3, x_in4);

input x_in1, x_in2, x_in3, x_in4;

output y_out;

assign y_out = x_in1 & x_in2 & x_in3 & x_in4;

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 5000)
#(PERIOD - 1)
$stop;
endmodule