系統時脈使用設計 啟用Compartor (二位元方式)

module top;

wire zA_lt_zB, zA_gt_zB, zA_eq_zB, A, B;
wire [1:0] zA, zB;

system_clock #50 s1(zA[1]);
system_clock #100 s2(zA[0]);
system_clock #200 s3(zB[1]);
system_clock #400 s4(zB[0]);

compare_2a X1(zA_lt_B, zA_gt_B, zA_eq_B, zA1, zA0, zB1, zB0);

endmodule

module compare_2a(A_lt_B, A_gt_B, A_eq_B, A, B);

input [1:0] A, B;
output A_lt_B, A_gt_B, A_eq_B;

assign A_lt_B= (A
assign A_gt_B= (A>B);

assign A_eq_B= (A==B);

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule