系統時脈使用設計 啟用Compartor (二位元方式)

module top;

wire zA_lt_zB, zA_gt_zB, zA_eq_zB, A, B;
wire [1:0] zA, zB;

system_clock #50 s1(zA[1]);
system_clock #100 s2(zA[0]);
system_clock #200 s3(zB[1]);
system_clock #400 s4(zB[0]);

compare_2a X1(zA_lt_B, zA_gt_B, zA_eq_B, zA1, zA0, zB1, zB0);

endmodule

module compare_2a(A_lt_B, A_gt_B, A_eq_B, A, B);

input [1:0] A, B;
output A_lt_B, A_gt_B, A_eq_B;

assign A_lt_B= (A
assign A_gt_B= (A>B);

assign A_eq_B= (A==B);

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule

系統時脈使用設計 啟用Compartor

module top;

wire zA_lt_zB, zA_gt_zB, zA_eq_zB, zA1, zA0, zB1, zB0;

system_clock #50 s1(zA1);
system_clock #100 s2(zA0);
system_clock #200 s3(zB1);
system_clock #400 s4(zB0);

compare_2a X1(zA_lt_B, zA_gt_B, zA_eq_B, zA1, zA0, zB1, zB0);

endmodule

module compare_2a(A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0);
input A1, A0, B1, B0;
output A_lt_B, A_gt_B, A_eq_B;
assign A_lt_B= (~A1)&B1|(~A1)&(~A0)&B0|(~A0)&B1&B0;

assign A_gt_B= A1&(~B1)|A0&(~B1)&(~B0)|A1&A0&(~B0);

assign A_eq_B= (~A1)&(~A0)&(~B1)&(~B0)|(~A0)&A0&(~B1)&B0|A1&A0&B1&B0|A1&(~A0)&B1&(~B0);

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule

<<時脈方式>>比較器

module top;

wire a0, a1, b0, b1;

system_clock #50 clock1(b0);
system_clock #100 clock1(b1);
system_clock #200 clock1(a0);
system_clock #400 clock1(a1);

comp io( out, a0, a1, b0, b1);
endmodule



module comp( out, a0, a1, b0, b1);

input a0, a1, b0, b1;
output out;
wire na0, na1, f1, f2, f3;

not(na0,a0);
not(na1,a1);
and i1( f1, na1, b1);
and i2( f2, na0, b1, b0);
and i3( f3, na0, na1, b0);
or i4( out, f1, f2, f3);

endmodule



module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 1000)
#(PERIOD - 1)
$stop;
endmodule

小老師實作例題

全加法器<<修改行為層>>.......原結構寫法((有截斷錯誤))

module top;

integer ia, ib, ic;
reg a, b, cin, s1, c1, c2, s, cout;

always
begin
#1
c1 = a & b;
s1 = a ^ b;
c2 = s1 & cin;
s = s1 ^ cin;
cout = c1 | c2;
end

initial
begin
for( ic = 0; ic <= 1; ic = ic + 1)
begin
cin = ic;
for( ia = 0; ia <= 1; ia = ia + 1)
begin
a = ia;
for( ib = 0; ib <= 1; ib = ib + 1)
begin
b = ib;
#100 $display("a = %d b = %d c = %d s = %d cout = %d", a, b, cin, s, cout);
end
end
end
end
endmodule

上課教材 Chap３

上課教材 Chap２

上課教材 Chap１

半加法器((系統時脈形式))

module top;

wire a, b, s, c;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

and a1( c, a, b);
xor x1( s, a, b);

endmodule


module system_clock(clk);

parameter PERLOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERLOD / 2)clk = ~clk;
#(PERLOD - PERLOD / 2)clk = ~clk;
end

always@(posedge clk)
if($time>1000)
#(PERLOD - 1)
$stop;
endmodule

半加法器((迴圈形式))

module top;
integer ia, ib;
reg a, b;
wire c, s;
and a1(c, a, b);
xor x1(s, a, b);
initial
begin
for(ia=0; ia<=1; ia=ia+1)
begin
a=ia;
for(ib=0; ib<=1; ib=ib+1)
begin
b=ib;
#30 $display("a=%d b=%d C=%d s=%d", a, b, c, s);
end
end
end
endmodule