<<時脈方式>>比較器

module top;

wire a0, a1, b0, b1;

system_clock #50 clock1(b0);
system_clock #100 clock1(b1);
system_clock #200 clock1(a0);
system_clock #400 clock1(a1);

comp io( out, a0, a1, b0, b1);
endmodule



module comp( out, a0, a1, b0, b1);

input a0, a1, b0, b1;
output out;
wire na0, na1, f1, f2, f3;

not(na0,a0);
not(na1,a1);
and i1( f1, na1, b1);
and i2( f2, na0, b1, b0);
and i3( f3, na0, na1, b0);
or i4( out, f1, f2, f3);

endmodule



module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 1000)
#(PERIOD - 1)
$stop;
endmodule