半加法器((系統時脈形式))

module top;

wire a, b, s, c;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

and a1( c, a, b);
xor x1( s, a, b);

endmodule


module system_clock(clk);

parameter PERLOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERLOD / 2)clk = ~clk;
#(PERLOD - PERLOD / 2)clk = ~clk;
end

always@(posedge clk)
if($time>1000)
#(PERLOD - 1)
$stop;
endmodule