系統時脈使用設計 啟用Compartor

module top;

wire zA_lt_zB, zA_gt_zB, zA_eq_zB, zA1, zA0, zB1, zB0;

system_clock #50 s1(zA1);
system_clock #100 s2(zA0);
system_clock #200 s3(zB1);
system_clock #400 s4(zB0);

compare_2a X1(zA_lt_B, zA_gt_B, zA_eq_B, zA1, zA0, zB1, zB0);

endmodule

module compare_2a(A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0);
input A1, A0, B1, B0;
output A_lt_B, A_gt_B, A_eq_B;
assign A_lt_B= (~A1)&B1|(~A1)&(~A0)&B0|(~A0)&B1&B0;

assign A_gt_B= A1&(~B1)|A0&(~B1)&(~B0)|A1&A0&(~B0);

assign A_eq_B= (~A1)&(~A0)&(~B1)&(~B0)|(~A0)&A0&(~B1)&B0|A1&A0&B1&B0|A1&(~A0)&B1&(~B0);

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule