須訂正

module top;
wire a0, a1, b0, b1;

initial begin

#50 a0=0; a1=0; b0=0; b1=0;
#50 a0=0; a1=0; b0=0; b1=1;
#50 a0=0; a1=0; b0=1; b1=0;
#50 a0=0; a1=0; b0=1; b1=1;
#50 a0=0; a1=1; b0=0; b1=0;
#50 a0=0; a1=1; b0=0; b1=1;
#50 a0=0; a1=1; b0=1; b1=0;
#50 a0=0; a1=1; b0=1; b1=1;
#50 a0=1; a1=0; b0=0; b1=0;
#50 a0=1; a1=0; b0=0; b1=1;
#50 a0=1; a1=0; b0=1; b1=0;
#50 a0=1; a1=0; b0=1; b1=1;
#50 a0=1; a1=1; b0=0; b1=0;
#50 a0=1; a1=1; b0=0; b1=1;
#50 a0=1; a1=1; b0=1; b1=0;
#50 a0=1; a1=1; b0=1; b1=1;
#50 $finish;

end
endmodule


module comparator(out, a0, a1, b0, b1);

input a0, a1, b0, b1;
output out;
wire na1, nb0, nb1, f1, f2, f3, f4,;

not(nb0,b0);
not(nb1,b1);
not(na1,a1);
and i1( f1, nb0, nb1);
and i2( f2, a0, nb0, nb1);
and i3( f3, a0, na1, nb0);
and i4( f4, a0, a1);
or i5( out, f1, f2, f3, f4);

endmodule

延遲 3 2 須訂正

module top;
reg zA, zB;
wire zO, zC1;
and a1(zC, zA, zB);
not a2(zO, zC);

initial begin

#100 zA=1; zB=0;
#100 zA=1; zB=1;
#100 zA=0; zB=1;
#100 zA=0; zB=0;
#100 $finish;

end
endmodule

module AND(C, A, B);
input A, B;
output C;
and (C, A, B);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(A=>C) = (Tpd_0_1, Tpd_1_0);
(B=>C) = (Tpd_0_1, Tpd_1_0);

endspecify
endmodule

module NOt(O, C);
input C;
output O;
not (O, C);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(C=>O) = (Tpd_0_1, Tpd_1_0);


endspecify
endmodule

Not AND(單腳)系統時脈

module top;
wire zA1, zB1;

system_clock #50 s1(zA1);

manf201 s3(zOut, zA1);
endmodule

module manf201(o, A1);
input A1;
output o;
not a2(o, A1);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(A1=>o) = (Tpd_0_1, Tpd_1_0);

endspecify
endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(49*PERIOD / 50) clk = ~clk;
#(PERIOD - 49*PERIOD / 50) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule

Not AND(雙腳)系統時脈

module top;
wire zA1, zB1;

system_clock #100 s1(zA1);
system_clock #200 s2(zB1);

manf201 s3(zOut, zA1, zB1);
endmodule

module manf201(o, A1, B1);
input A1, B1;
output o;
nand a1(o, A1, B1);

specify
specparam

Tpd_0_1 = 1.13 : 3.09 : 7.75,
Tpd_1_0 = 0.93 : 2.50 : 7.34;
(A1=>o) = (Tpd_0_1, Tpd_1_0);
(B1=>o) = (Tpd_0_1, Tpd_1_0);

endspecify
endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule

RTL <<演算法>> 系統時脈

module top;

wire out;
wire[3:0] in;

system_clock #50 o1(in[0]);
system_clock #100 o2(in[1]);
system_clock #200 o3(in[2]);
system_clock #400 o4(in[3]);

and4_algo v1( out, in);

endmodule


module and4_algo(y_out,x_in);

input[3:0] x_in;
output y_out;
reg y_out;
integer k;

always@(x_in)
begin:and_loop
y_out = 1;
for(k = 0;k <= 3;k = k + 1)
if(x_in[k]==0)
begin
y_out=0;
disable and_loop;
end
end
endmodule


module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule

RTL 結構做法 ~系統時脈~

module top;
wire [3:0] zin;
wire zout;

system_clock #100 s1(zin[0]);
system_clock #200 s2(zin[1]);
system_clock #300 s2(zin[2]);
system_clock #400 s2(zin[3]);

and4_rtl s5(zout, zin);

endmodule

module and4_rtl(y_out, x_in);

input [3:0] x_in;
output y_out;
wire w1, w2;
and a1(w1, x_in[0], x_in[1]);
and a2(w2, x_in[2], x_in[3]);
and a2(y_out, w1, w2);

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule

RTL 矩陣形式 ~系統時脈~

module top;
wire [3:0] zin;
wire zout;

system_clock #100 s1(zin[0]);
system_clock #200 s2(zin[1]);
system_clock #300 s2(zin[2]);
system_clock #400 s2(zin[3]);

and4_rtl s5(zout, zin);

endmodule

module and4_rtl(y_out, x_in);

input [3:0] x_in;

output y_out;

assign y_out = &x_in;

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 6000)
#(PERIOD - 1)
$stop;
endmodule

RTL~系統時脈~

module top;
wire zin1, zin2, zin3, zin4;

system_clock #100 s1(zin1);
system_clock #200 s2(zin2);
system_clock #300 s3(zin3);
system_clock #400 s4(zin4);

and4_rtl s5(zout, zin1, zin2, zin3, zin4);

endmodule

module and4_rtl(y_out, x_in1, x_in2, x_in3, x_in4);

input x_in1, x_in2, x_in3, x_in4;

output y_out;

assign y_out = x_in1 & x_in2 & x_in3 & x_in4;

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 5000)
#(PERIOD - 1)
$stop;
endmodule

系統時脈使用設計 啟用Compartor (二位元方式)

module top;

wire zA_lt_zB, zA_gt_zB, zA_eq_zB, A, B;
wire [1:0] zA, zB;

system_clock #50 s1(zA[1]);
system_clock #100 s2(zA[0]);
system_clock #200 s3(zB[1]);
system_clock #400 s4(zB[0]);

compare_2a X1(zA_lt_B, zA_gt_B, zA_eq_B, zA1, zA0, zB1, zB0);

endmodule

module compare_2a(A_lt_B, A_gt_B, A_eq_B, A, B);

input [1:0] A, B;
output A_lt_B, A_gt_B, A_eq_B;

assign A_lt_B= (A
assign A_gt_B= (A>B);

assign A_eq_B= (A==B);

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule

系統時脈使用設計 啟用Compartor

module top;

wire zA_lt_zB, zA_gt_zB, zA_eq_zB, zA1, zA0, zB1, zB0;

system_clock #50 s1(zA1);
system_clock #100 s2(zA0);
system_clock #200 s3(zB1);
system_clock #400 s4(zB0);

compare_2a X1(zA_lt_B, zA_gt_B, zA_eq_B, zA1, zA0, zB1, zB0);

endmodule

module compare_2a(A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0);
input A1, A0, B1, B0;
output A_lt_B, A_gt_B, A_eq_B;
assign A_lt_B= (~A1)&B1|(~A1)&(~A0)&B0|(~A0)&B1&B0;

assign A_gt_B= A1&(~B1)|A0&(~B1)&(~B0)|A1&A0&(~B0);

assign A_eq_B= (~A1)&(~A0)&(~B1)&(~B0)|(~A0)&A0&(~B1)&B0|A1&A0&B1&B0|A1&(~A0)&B1&(~B0);

endmodule

module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 10000)
#(PERIOD - 1)
$stop;
endmodule

<<時脈方式>>比較器

module top;

wire a0, a1, b0, b1;

system_clock #50 clock1(b0);
system_clock #100 clock1(b1);
system_clock #200 clock1(a0);
system_clock #400 clock1(a1);

comp io( out, a0, a1, b0, b1);
endmodule



module comp( out, a0, a1, b0, b1);

input a0, a1, b0, b1;
output out;
wire na0, na1, f1, f2, f3;

not(na0,a0);
not(na1,a1);
and i1( f1, na1, b1);
and i2( f2, na0, b1, b0);
and i3( f3, na0, na1, b0);
or i4( out, f1, f2, f3);

endmodule



module system_clock(clk);

parameter PERIOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERIOD / 2) clk = ~clk;
#(PERIOD - PERIOD / 2) clk = ~clk;
end

always@(posedge clk)
if($time > 1000)
#(PERIOD - 1)
$stop;
endmodule

小老師實作例題

全加法器<<修改行為層>>.......原結構寫法((有截斷錯誤))

module top;

integer ia, ib, ic;
reg a, b, cin, s1, c1, c2, s, cout;

always
begin
#1
c1 = a & b;
s1 = a ^ b;
c2 = s1 & cin;
s = s1 ^ cin;
cout = c1 | c2;
end

initial
begin
for( ic = 0; ic <= 1; ic = ic + 1)
begin
cin = ic;
for( ia = 0; ia <= 1; ia = ia + 1)
begin
a = ia;
for( ib = 0; ib <= 1; ib = ib + 1)
begin
b = ib;
#100 $display("a = %d b = %d c = %d s = %d cout = %d", a, b, cin, s, cout);
end
end
end
end
endmodule

上課教材 Chap３

上課教材 Chap２

上課教材 Chap１

半加法器((系統時脈形式))

module top;

wire a, b, s, c;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

and a1( c, a, b);
xor x1( s, a, b);

endmodule


module system_clock(clk);

parameter PERLOD = 100;
output clk;
reg clk;

initial
clk = 0;

always
begin
#(PERLOD / 2)clk = ~clk;
#(PERLOD - PERLOD / 2)clk = ~clk;
end

always@(posedge clk)
if($time>1000)
#(PERLOD - 1)
$stop;
endmodule

半加法器((迴圈形式))

module top;
integer ia, ib;
reg a, b;
wire c, s;
and a1(c, a, b);
xor x1(s, a, b);
initial
begin
for(ia=0; ia<=1; ia=ia+1)
begin
a=ia;
for(ib=0; ib<=1; ib=ib+1)
begin
b=ib;
#30 $display("a=%d b=%d C=%d s=%d", a, b, c, s);
end
end
end
endmodule

行為層作法

module top;

integer ia, ib;
reg a, b;
wire c;

xor x1(c,a,b);

initial
begin
for(ia = 0;ia <= 1;ia = ia + 1)
begin
a=ia;
for(ib = 0;ib <= 1;ib = ib + 1)
begin
b=ib;
#10 $display("a = %d b = %d c = %d", a, b, c);
end
end
end
endmodule

系統時脈模組

１module mux(OUT, A, B, SEL);
２output OUT;
３input A, B, SEL;
４
５not I5 (sel_n SEL);
６and I6 (sel_a, A, SEL);
７and I7 (sel_b, sel_n, B);
８
９or I4 (out, sel_a, sel_b);
10 endmodule

使用Verilog基礎語言

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
always#1 c=a&b;
endmodule
module system_clock(clk);
parameter PERIOD=100;output clk;
reg clk;initialclk=0;
alwaysbegin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
endalways@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule